Advanced IC Packaging Is Next Front In The Chip Wars

CoWoS is a 2.5-dimensional (2.5D) packaging technology developed by TSMC for high-performance ICs used in computing, data centers and telecom equipment. As can be seen in the diagram below, it utilizes through-silicon via (TSV) vertical electrical connections and a silicon interposer.

According to Cadence Design Systems, a leading electronic design automation company, CoWoS“is particularly well-suited for artificial intelligence (AI) accelerators, where multiple types of chips need to work together efficiently” – including high-bandwidth memory (HBM).

As noted by AMD,“HBM is a new type of memory chip with low power consumption and ultra-wide communication lanes. It uses vertically stacked memory chips interconnected by microscopic wires called through-silicon vias, or TSVs.”

Cadence explains that“2.5D packaging... is an intermediate step between traditional 2D packaging and full-fledged 3D packaging. In 2.5D packaging, multiple semiconductor dies, typically from different process technologies, are placed side by side on a silicon interposer. The interposer acts as a bridge, connecting the individual dies and providing a high-speed communication interface.”

This“enables the integration of diverse components, such as processors, memory, and sensors, on a single package. This proximity results in reduced interconnect lengths, leading to improved signal integrity and lower latency.”

In addition, it reduces both the size of the package and power consumption and facilitates heat dissipation.

As it ramps up CoWoS production capacity, TSMC should be able to catch up with the backlog of orders for Nividia's H100 processors and be ready to roll out its new Blackwell B200 processors, expected to start early next year.

Brian Wang of NextBigFuture calculates that the B200 is four times faster and 25 times more efficient than the H100. What users and analysts will say about its overall AI performance won't be known until sometime next year, but it substantially raises the bar for Huawei. However, it will almost certainly not be sold in China.

TSMC introduced the first version of CoWoS in 2012. As recently reported in a Chinese news site Guancha (Observer Net) article, Huawei's IC design division HiSilicon“conducted a comprehensive assessment of CoWoS in 2014, including cost and yield, and decided to take the lead” in adopting the technology.

Starting with the integration of 16nm logic chips and 28nm Input-Output (I/O) chips, Huawei HiSilicon worked with TSMC all the way to 7nm in 2019. That progress ended in 2020 when the US sanctioned Huawei and forced TSMC to cut it off.

But Huawei already had years of experience implementing the concept, in which the components combined in a system-on-chip are generally referred to as“chiplets.” AMD, Apple, Intel and Nvidia all use chiplet design. IBM explains it as follows:

Huawei/HiSilicon has reportedly amassed hundreds of patents covering chiplet technology. In 2021, Shenzhen-based Chipuller acquired 28 from failed Silicon Valley venture company Glue.

Chipuller CEO Yang Meng told Reuters that, with chiplets,“US-China competition is on the same starting line. In other (chip technologies) there is a sizeable gap between China and the United States, Japan, South Korea, Taiwan.”

But chiplets enable the Chinese to circumvent the US restrictions on exports of advanced semiconductor production equipment that have so far prevented them from advancing beyond 5nm.

China has a very large and advanced IC packaging industry. Two of the world's top five outsourced semiconductor assembly and test (OSAT) companies – JCET, which ranks third, and Tongfu Microelectronics, which ranks fourth – are Chinese, while Beijing ESWIN and other smaller companies are also developing chiplet technology.

Tongfu is unique in that it has provided OSAT services to AMD for many years and operates joint-venture factories with it in Suzhou and Penang.

The Chinese government sees advanced IC packaging in general and chiplets in particular as key to overcoming US sanctions and making the Chinese semiconductor industry both competitive and independent.

The US government, which also regards advanced IC packaging as crucial, plans to subsidize the construction of Amkor's first OSAT facility in the US. Amkor, the world's second-largest OSAT company, is based in Arizona.

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In late July, US Commerce Secretary Gina Raimondo said,“One of the fundamental goals of the CHIPS and Science Act is creating an advanced packaging ecosystem in the US to ensure full start to finish chip production occurs domestically... The leading-edge chips that will be packaged right here in Arizona are foundational to technologies of the future that will define global economic and national security for decades to come.”

Source: IDC data, Asia Times chart

The Biden administration, pressed by China hawks in Congress, has reportedly been considering the restriction of chip assembly and packaging equipment exports to China. But it does not appear to have made much progress so far, perhaps because most of this equipment is made in Japan.

Japan has apparently resisted the latest US request to further tighten sanctions on China, but the Chinese are apparently taking no chances. In addition to advanced packaging processes, they are developing their own dicing, wire bonding, test and other assembly, packaging and test equipment.

At its Japan 3DIC R&D Center located in the science city of Tsukuba northeast of Tokyo, TSMC is developing advanced 3D packaging technology with more than 20 leading Japanese materials and equipment companies.

While the US frets about Chinese chiplets, they are moving on from 2.5D CoWoS to make the 2nm fabs that TSMC is now building in Taiwan 3D capable and prepare for smaller process nodes already under development.

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