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Polyu Develops Quantum-Tunnelling Field-Effect Transistor To Overcome Barriers To Integrated-Circuit Chip Development
(MENAFN- Media OutReach Newswire) -share-copy-box" class="mo-ui-news-article-share-copy-box" hidden>HONG KONG SAR –
Media OutReach Newswire – 31 August 2026 – The next generation of microelectronics relies on improvements in transistor switching performance to advance computing power. However, conventional semiconductor technology has hit the physical“Boltzmann limit”, which restricts the energy efficiency of traditional transistors. A research team at The Hong Kong Polytechnic University (PolyU) has engineered a novel tunnelling field-effect transistor (TFET) utilising 2D nanomaterials. The breakthrough can offer the fundamentals for energy-efficient computing and next-generation AI chips.
The research was led by Prof. Jianhua HAO, Head of the Department of Physics and Materials and Chair Professor of Materials Physics and Devices at PolyU, in collaboration with the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design. The findings have been published in the prestigious scientific journal Science.
Conventional transistors rely on thermionic emission of electrical charges, which requires a minimum gating voltage of 60 millivolts (mV). However, the“Boltzmann limit” makes subthreshold swing values below 60 mV decade−1 at room temperature physically impossible, limiting progress in high-performance electronics.
Prof. Hao said,“By adopting quantum tunnelling, our TFET breaks through this boundary, paving the way for ultra-low-power, high-performance integrated circuits essential for emerging AI chips and advanced semiconductor applications.”
Prof. Hao's team created ultra-thin heterostructure of 2D bismuth and indium selenide alternating layers using pulsed laser deposition. By exercising precise control over the layer structure, the normally semi-metallic bismuth transforms into a semiconductor in 2D form, allowing charge carriers to tunnel efficiently into indium selenide through quantum tunnelling mechanism.
The resulting TFET achieved SS values well below the 60 mV decade−1 limit. Operating at room temperature on silicon substrates, the device required a gate-voltage range of only 160 mV-far lower than the 800 mV originally required.
The device resolved a challenge in experimental TFETs by delivering a high output current alongside an exceptionally high ON/OFF current ratio, which helps drive multiple downstream logic gates and diminish circuit-delay.
The research was led by Prof. Jianhua HAO, Head of the Department of Physics and Materials and Chair Professor of Materials Physics and Devices at PolyU, in collaboration with the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design. The findings have been published in the prestigious scientific journal Science.
Conventional transistors rely on thermionic emission of electrical charges, which requires a minimum gating voltage of 60 millivolts (mV). However, the“Boltzmann limit” makes subthreshold swing values below 60 mV decade−1 at room temperature physically impossible, limiting progress in high-performance electronics.
Prof. Hao said,“By adopting quantum tunnelling, our TFET breaks through this boundary, paving the way for ultra-low-power, high-performance integrated circuits essential for emerging AI chips and advanced semiconductor applications.”
Prof. Hao's team created ultra-thin heterostructure of 2D bismuth and indium selenide alternating layers using pulsed laser deposition. By exercising precise control over the layer structure, the normally semi-metallic bismuth transforms into a semiconductor in 2D form, allowing charge carriers to tunnel efficiently into indium selenide through quantum tunnelling mechanism.
The resulting TFET achieved SS values well below the 60 mV decade−1 limit. Operating at room temperature on silicon substrates, the device required a gate-voltage range of only 160 mV-far lower than the 800 mV originally required.
The device resolved a challenge in experimental TFETs by delivering a high output current alongside an exceptionally high ON/OFF current ratio, which helps drive multiple downstream logic gates and diminish circuit-delay.
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